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rej03f0250-0200 rev.2.00 sep 14, 2007 page 1 of 13 M66256FP 5120 8-bit line memory (fifo) rej03f0250-0200 rev.2.00 sep 14, 2007 description the M66256FP is a high-speed line memory with a fifo (first in first out) structure of 5120-word 8-bit configuration which uses high-performance silicon gate cmos process technology. it has separate clock, enable and reset signals for write and read, and is most suitable as a buffer memory between devices with different data processing throughput. features ? memory configuration: 5120 words 8 bits (dynamic memory) ? high-speed cycle: 25 ns (min) ? high-speed access: 18 ns (max) ? output hold: 3 ns (min) ? fully independent, asynchronous write and read operations ? variable length delay bit ? output: 3 states application digital photocopiers, high-speed facsimile, laser beam printers. block diagram 7 18 read address counter write address counter read control circuit write control circuit input buffer memory array of 5120-word 8-bit configuration 5 6 8 13 14 15 16 21 22 24 23 1 2 3 4 9 10 11 12 20 19 17 re rres rck read enable input read reset input read clock input write enable input data input d 0 to d 7 data output q 0 to q 7 write reset input write clock input gnd we wres wck v cc output buffer
M66256FP rej03f0250-0200 rev.2.00 sep 14, 2007 page 2 of 13 pin arrangement 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 d 0 d 1 d 2 d 3 we wres v cc wck d 4 d 5 d 6 d 7 q 0 q 1 q 2 q 3 re rres gnd rck q 4 q 5 q 6 q 7 data input data output data output data input M66256FP (top view) outline: 24p2u-a read enable input read reset input read clock input write enable input write clock input write reset input
M66256FP rej03f0250-0200 rev.2.00 sep 14, 2007 page 3 of 13 absolute maximum ratings (ta = 0 to 70 c, unless otherwise noted) item symbol ratings unit conditions supply voltage v cc ? 0.5 to +7.0 v input voltage v i ? 0.5 to v cc + 0.5 v output voltage v o ? 0.5 to v cc + 0.5 v a value based on gnd pin power dissipation pd 440 mw ta = 25 c storage temperature tstg ? 65 to 150 c recommended operating conditions item symbol min typ max unit supply voltage v cc 4.5 5 5.5 v supply voltage gnd ? 0 ? v operating ambient temperature topr 0 ? 70 c electrical characteristics (ta = 0 to 70 c, v cc = 5 v 10%, gnd = 0 v) item symbol min typ max unit test conditions "h" input voltage v ih 2.0 ? ? v "l" input voltage v il ? ? 0.8 v "h" output voltage v oh v cc ? 0.8 ? ? v i oh = ? 4 ma "l" output voltage v ol ? ? 0.55 v i ol = 4 ma "h" input current i ih ? ? 1.0 a v i = v cc we , wres , wck, re , rres , rck, d 0 to d 7 "l" input current i il ? ? ? 1.0 a v i = gnd we , wres , wck, re , rres , rck, d 0 to d 7 off state "h" output current i ozh ? ? 5.0 a v o = v cc off state "l" output current i ozl ? ? ? 5.0 a v o = gnd operating mean current dissipation i cc ? ? 80 ma v i = v cc , gnd, output open t wck , t rck = 25 ns input capacitance c i ? ? 10 pf f = 1 mhz off state output capacitance c o ? ? 15 pf f = 1 mhz function when write enable input we is "l", the contents of data inputs d 0 to d 7 are written into memory in synchronization with rise edge of write clock input wck. at this time, the write address counter is also incremented simultaneously. the write function given below are also performed in synchronization with rise edge of wck. when we is "h", a write operation to memory is inhibited and the write address counter is stopped. when write reset input wres is "l", the write address counter is initialized. when read enable input re is "l", the contents of memory are output to data outputs q 0 to q 7 in synchronization with rise edge of read clock input rck. at this time, the read address counter is also incremented simultaneously. the read functions given below are also performed in synchronization with rise edge of rck. when re is "h", a read operation from memory is inhibited and the read address counter is stopped. the outputs are in the high impedance state. when read reset input rres is "l", the read address counter is initialized.
M66256FP rej03f0250-0200 rev.2.00 sep 14, 2007 page 4 of 13 switching characteristics (ta = 0 to 70 c, v cc = 5 v 10%, gnd = 0 v) item symbol min typ max unit access time t ac ? ? 18 ns output hold time t oh 3 ? ? ns output enable time t oen 3 ? 18 ns output disable time t odis 3 ? 18 ns timing conditions (ta = 0 to 70 c, v cc = 5 v 10%, gnd = 0 v, unless otherwise noted) item symbol min typ max unit write clock (wck) cycle t wck 25 ? ? ns write clock (wck) "h" pulse width t wckh 11 ? ? ns write clock (wck) "l" pulse width t wckl 11 ? ? ns read clock (rck) cycle t rck 25 ? ? ns read clock (rck) "h" pulse width t rckh 11 ? ? ns read clock (rck) "l" pulse width t rckl 11 ? ? ns input data setup time to wck t ds 7 ? ? ns input data hold time to wck t dh 3 ? ? ns reset setup time to wck or rck t ress 7 ? ? ns reset hold time to wck or rck t resh 3 ? ? ns reset nonselect setup time to wck or rck t nress 7 ? ? ns reset nonselect hold time to wck or rck t nresh 3 ? ? ns we setup time to wck t wes 7 ? ? ns we hold time to wck t weh 3 ? ? ns we nonselect setup time to wck t nwes 7 ? ? ns we nonselect hold time to wck t nweh 3 ? ? ns re setup time to rck t res 7 ? ? ns re hold time to rck t reh 3 ? ? ns re nonselect setup time to rck t nres 7 ? ? ns re nonselect hold time to rck t nreh 3 ? ? ns input pulse rise/fall time tr, tf ? ? 20 ns data hold time * t h ? ? 20 ms notes: perform reset operation after turning on power supply. * for 1-line access, the following should be satisfied: we "h" level period 20 ms ? 5120 t wck ? wres "l" level period re "h" level period 20 ms ? 5120 t rck ? rres "l" level period
M66256FP rej03f0250-0200 rev.2.00 sep 14, 2007 page 5 of 13 test circuit c l = 30 pf: t ac , t oh qn c l = 5 pf: t oen , t odis sw1 sw2 r l = 1 k ? r l = 1 k ? v cc qn input pulse level: 0 to 3v input pulse rise/fall time: 3 ns decision voltage input: 1.3 v decision voltage output: 1.3 v (however, t odis (lz) is 10% of output amplitude and t odis (hz) is 90% of that for decision) the load capacitance c l includes the floating capacitance of connection and the input capacitance of probe. parameter sw1 sw2 t odis (lz) closed open t odis (hz) open closed t oen (zl) closed open t oen (zh) open closed t odis /t oen test condition rck re qn qn v ol v oh gnd 3 v gnd 3 v 1.3 v 1.3 v 1.3 v t oen (zh) t oen (zl) 1.3 v 90% 10% t odis (hz) t odis (lz)
M66256FP rej03f0250-0200 rev.2.00 sep 14, 2007 page 6 of 13 operating timing write cycle wck we dn t ds t wck cycle n cycle n + 1 cycle n + 2 (n) (n + 1) (n + 2) (n + 3) wres = "h" (n + 4) cycle n + 3 cycle n + 4 disable cycle t wckh t weh t nwes t nweh t wes t wckl t dh t ds t dh write reset cycle wck wres dn t ds t wck cycle n ? 1 cycle n (n ? 1) (n) (0) (1) we = "l" (2) cycle 1 cycle 0 cycle 2 reset cycle t nresh t resh t nress t ress t dh t ds t dh
M66256FP rej03f0250-0200 rev.2.00 sep 14, 2007 page 7 of 13 matters that needs attention when wck stops wck we dn t wck period for writing data (n) into memory period for writing data (n) into memory t nwes n cycle n cycle disable cycle n + 1 cycle (n) (n) wres = "h" t ds t dh t ds t dh input data of n cycle is read at the rising edge after wck of n cycle and writing operation starts in the wck low-level period of n + 1 cycle. the writing operation is co mplete at the falling edge after n + 1 cycle. to stop reading write data at n cycle, enter wck before the rising edge after n + 1 cycle. when the cycle next to n cycle is a disable cycle, wck for a cycle requires to be entered after the disable cycle as well.
M66256FP rej03f0250-0200 rev.2.00 sep 14, 2007 page 8 of 13 read cycle rck re qn t rck cycle n cycle n + 1 cycle n + 2 (n) (n + 1) (n + 2) (n + 3) rres = "h" (n + 4) cycle n + 3 cycle n + 4 disable cycle high-z t rckh t reh t nres t nreh t res t ac t rckl t odis t oen t oh read reset cycle rck rres qn t rck cycle n ? 1 cycle n (n ? 1) (n) (0) (0) (0) (1) re = "l" (2) cycle 1 cycle 0 cycle 2 reset cycle t nresh t resh t nress t ac t oh t ress
M66256FP rej03f0250-0200 rev.2.00 sep 14, 2007 page 9 of 13 variable length delay bits 1-line (5120 bits) delay a write input data is written into memory at the second rise edge of wck in the cycle, and a read output data is output from memory at the first rise edge of rck in the cycle, so that 1-line delay can be made easily. wck rck dn qn wres rres (5117) (5118) (5119) (2) (1) (0) we , re = "l" (0') (1') (2') (3') t resh t ress t dh t ds t dh t oh t ac 5120 cycles t ds cycle 1 cycle 0 cycle 5118 cycle 5119 cycle 5120 (0') cycle 5121 (1') cycle 5122 (2') cycle 2 (0) (1) (2) (3) n-bit delay bit (making a reset at a cycle corresponding to delay length) wck rck dn qn wres rres (n ? 3) (n ? 2) (n ? 1) (2) (1) (0) we , re = "l" m 3 (0') (1') (2') (3') t resh t ress t dh t ds t dh t oh t ac m cycles t ds t resh t ress cycle 1 cycle 0 cycle n ? 2 cycle n ? 1 cycle n (0') cycle n + 1 (1') cycle n + 2 (2') cycle n + 3 (3') cycle 2 (0) (1) (2) (3)
M66256FP rej03f0250-0200 rev.2.00 sep 14, 2007 page 10 of 13 n-bit delay 2 (sliding wres and rres at a cycle corresponding to delay length) wck rck dn qn wres (n ? 2) (n ? 1) (n) (2) (1) (0) we , re = "l" m 3 (n + 1) (n + 2) (n + 3) t resh t ress t dh t ds t dh t oh t ac m cycles t ds cycle 1 cycle 0 cycle n ? 1 cycle n cycle n + 1 cycle n + 2 cycle n + 3 cycle 2 cycle n ? 2 (0) (1) (2) (3) rres t resh t ress n-bit delay 3 (disabling re at a cycle corresponding to delay length) wck rck dn qn wres rres (n ? 2) (n ? 1) (n) (2) (1) (0) we = "l" m 3 (n + 1) (n + 2) (n + 3) t resh t ress t dh t ds t dh t oh t ac m cycles high-z t ds cycle 1 cycle 0 cycle n ? 1 cycle n cycle n + 1 cycle n + 2 cycle n + 3 cycle 2 (0) (1) (2) (3) re t res t nreh
M66256FP rej03f0250-0200 rev.2.00 sep 14, 2007 page 11 of 13 shortest read of data "n" written in cycle n (cycle n ? 1 on read side should be started after end of cycle n + 1 on write side) when the start of cycle n ? 1 on read side is earlier than the end of cycle n + 1 on write side, output qn of cycle n becomes invalid. in the figure shown below, the read of cycle n ? 1 is invalid. (n) (n + 1) (n + 2) (n + 3) cycle n cycle n + 1 cycle n ? 2 cycle n ? 1 cycle n (n) invalid cycle n + 2 cycle n + 3 wck dn qn rck longest read of data "n" written in cycle n: 1-line delay (cycle n <1>* on read side should be started when cycle n <2>* on write is started) output qn of n cycle <1>* can be read until the start of reading side n cycle <1>* and the start of writing side n cycle <2>* overlap each other. cycle n <1> * (n) <1> * (n) <0> * (n) <2> * (n) <1> * (00) <2> * (0) <1> * (n ? 1) <1> * (n ? 1) <0> * (n ? 1) <2> * (n ? 1) <1> * wck dn qn rck cycle n <0> * cycle 0 <2> * cycle 0 <1> * cycle n <2> * cycle n <1> * note: <0>*, <1>* and <2>* indicates a line value.
M66256FP rej03f0250-0200 rev.2.00 sep 14, 2007 page 12 of 13 application example laplacian filter circuit for correction of r esolution in the secondary scanning direction m66256 2 corrected image data primary scanning direction line (n ? 1) n' = n + k { (n ? a) + (n ? b) } = n + k {2n ? (a + b)} k: laplacian coefficient a n b line n line (n + 1) k 1-line delay d 0 to d 7 q 0 to q 7 m66256 a line (n ? 1) image data b line (n + 1) image data adder a + b subtractor 2n ? (a + b) adder n + k {2n ? (a + b) } n line n image data 1-line delay d 0 to d 7 q 0 to q 7 secondary scanning direction
M66256FP rej03f0250-0200 rev.2.00 sep 14, 2007 page 13 of 13 package dimensions ssop24-p-375-0.80 ? jedec code 0.4 24p2u-a plastic 24pin 375mil ssop symbol min nom max a a 2 b c d e l l 1 y dimension in millimeters h e a 1 i 2 ? ? 0.3 0.1 0.23 10.2 7.4 10.0 0.5 1.27 0.2 ? ?? ?? ? ? ?? ?? ?? ?? ?? ?? .3 2 0.35 0.25 10.3 7.5 0.8 10.3 0.7 1.4 9.53 0.3 2.65 0.45 0.3 10.4 7.6 10.6 0.9 0.1 b 2 0.5 0 8 e e 1 24 13 12 1 h e e d e y f a a 2 a 1 l 1 l c e b 2 e 1 i 2 recommended mount pad detail f z z 1 detail g z 1 0.75 0.9 z b g eiaj package code weight(g) lead material cu alloy
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